1. Field of the Invention
The present invention relates to a packet transmission control apparatus for transmitting a packet read from a random access memory (RAM) equipped in a system controller to an interface on transmission side.
2. Description of the Related Art
FIG. 1 is an outline diagram showing the configuration of a conventional multi-computer system. In FIG. 1, the computer systems are respectively named the system-0 and system-1 computer systems, categorized by the numbers, “0” and “1”, that are assigned to system controllers (SC) 10 and 20.
The configurations of the system-0 and system-1 computer systems are the same and therefore the configuration of the system-0 computer system is briefly described in the following. In the system-0 computer system, a first CPU 1 and a second CPU 2 are connected to a system controller SC0 (10), to which a plurality of DIMMs (dual inline memory modules) 4 and 6 are respectively connected by way of first and second media access controllers (MACs) 3 and 5. Further, the system-0 computer system and the system-1 computer system are interconnected by way of system controllers SC10 and SC20.
A random access memory (RAM) (not shown in a drawing herein) is provided in each of the system controllers SC10 and SC20, so that packets read out from the RAM are transmitted to a correspondent by way of an interface (not shown in the drawing herein).
FIG. 2 shows a conventional packet transmission control apparatus. The packet transmission control apparatus reads out a packet using one controller CNTL from a RAM provided in the system controller SC10, and transmits it to a correspondent node through an interface (not shown). As shown in FIG. 2, the conventional packet transmission control apparatus includes a controller unit (CNTL) 30, a BUSY control circuit 40, and a RAM (memory) 50. The controller unit 30 controls the transmission of a packet to an interface (IF) unit, and manages a data request to the RAM 50 and data reception from the RAM 50. The BUSY control circuit 40 recognizes the BUSY state of a control unit (not shown in the drawing herein) of a packet destination. The RAM 50 stores data to be requested.
The controller unit (CNTL) 30 shown in FIG. 2, equipped with a STM (state-machine) 31 (refer to reference patent document 1), controls the timing of a request to the RAM 50, receives data from the RAM 50, detects the data length and errors, and prepares a packet to be transmitted on the basis of the data stored in the RAM. The STM 31 shifts states by means of a control signal or predetermined timing, and manages the process carried out in the state. Note that the controller unit (CNTL) 30 includes latches 32 and 33 for exchanging data with the RAM 50.
Further, the BUSY control circuit 40 judges the packet processing state of an interface at the correspondent on the basis of a signal sent from the interface, and instructs the STM 31 to stop transmitting data if the BUSY control circuit 40 recognizes a BUSY state.
The RAM 50 stores data to be requested. When a readout request with a read address is given, the RAM 50 reads out the requested data according to the read address.
Next is a description of the operation of the conventional packet transmission control apparatus, using the time chart shown in FIG. 3. Referring to FIG. 3, when a data request is enabled, the STM 31 of the CNTL 30 is activated and the state is shifted from an IDLE (00) to an ST0. When the CNTL 30 sends a readout request (REQ to RAM) to the RAM 50, the STM 31 shifts from the ST0 to ST1 and waits for a request permission signal (VLD (valid) from RAM) from the RAM 50. When the request permission signal (VLD from RAM) is issued from the RAM 50, it prepares to read data, while the STM 31 of the CNTL 30 shifts from the ST1 to ST2 and prepares to receive data (READ DATA). The CNTL 30 receives the data (READ DATA) from the RAM 50 and transmits the DATA to the IF unit (output DATA to IF) in association with the STM 31 shifting from the ST2 to ST3. Upon completion of transmitting the data, the STM 31 ends the operation and returns to the initial state to repeat the request for data. If a BUSY occurs, the BUSY control circuit 40 sends a control signal to the STM 31 so as to stop transmitting data. When the control signal is cancelled, the STM 31 resumes its operation in order to transmit data.
The above described packet transmission control apparatus uses one controller to process requests and therefore there must be a wait until one process is completed before the next request is processed. In order to solve this problem, it is conceivable to design a timing control circuit for a RAM readout controller to control packets without time gap. The timing control circuit calculates a readout latency from RAM including waiting period for arbitration between readout requests to RAM, and the timing of completion of data transmission and restart of transmission by reflecting BUSY of interface of data destination side. There is a problem with such a design, however, in that it requires complex control mechanisms and thus a substantial number of difficulties need to be overcome to implement it.
Patent document 1: Laid-Open Japanese Patent Application Publication No. 2001-337861 (paragraph 4, line 15 through paragraph 7, line 2; and FIGS. 1 and 4)